DEPARTMENT OF ELECTRICAL AND COMPUTING ENGINEERING TECHNOLOGY

ECET 146 Home Page

NOTE: THE CLASS NOW MEETS IN ET305 INSTEAD OF KT250

ECET 146, Class 2, Lab 2, Credit 3

P:111, C: 114 or CS 114. Basic Digital system techniques with emphasis on programable logic and ASIC theory. Computer-aided design is strongly emphased along with system considerations such as criteria for device selection, testablity and vendor selection.

• Lab 1 - see the end of Week 2 slides
• Week 10 - Washing Machine (due 4/1)

• Understanding of basic concepts of programmable logic

• Understand various types of programmable logic devices such as Field Programmable Gate Arrays, Masked Gate Arrays, Standard Cell, and Full Custom Chips

• To be able to use an industry standard digital design package such as Altera’s Max Plus or Xilinx’s ISE Foundation

• Learn to use different design entry techniques, including schematic, waveform, state machine diagrams, and text hardware design languages

• Work in teams to solve complex design problems
  

• Present written and oral reports representing solutions to design problems
  

• Week 1
• Week 2
• Week 3
• Week 4
• Week 5
• Week 5b
• Week 6
• Week 7 (Midterm Project)
• Final Project - Due May 1, 2009

timedelay.tdf (right click and select save target)

Lab Report Format

Sample Report

Week 3 Demo Part One

TimeDelay Design File

Sample Stoplight VHDL File